CMOS Quad Clocked D Latch TI Ic CD4042B CD4076B CD4508B CD54AC573 CD54ACT373
Category:
Circuitos integrados
In-stock:
em estoque
Price:
Negotiated
Payment Method:
T/T, União Ocidental
Specifications
categoria:
Circuitos Componente-integrados eletrônicos (IC)
Descrição:
Os tipos CD4042B contêm quatro circuitos de trava, cada um estroboscópico por um
Nome de parte similar:
CD4042B CD4076B CD4508B CD54AC573 CD54ACT373
Série:
Travas tipo D-COMS
Família:
Flip-flops, travas e registradores IC
Pacote:
Montagem em superfície/furo embora
Status livre de chumbo:
RoHS complacente, PB livre, sem chumbo
Temperatura operacional:
-40 ° C ~ 85 ° C.
Destacar:
Circuitos Integrados CD4076B CI
,Circuitos Integrados CD4042B CI
,Circuitos Integrados CD4508B CI
Introdução
CD4042B CD4076B CD4508B CD54AC573 CD54ACT373 CMOS Quad Clocked D Latch TI Ic componentes
Circuitos integrados IC Texas Instruments(Componentes eletrónicos)
CD4042B CD4076B CD4508B CD54AC573 CD54ACT373 CMOS Quad Clocked D Latch TI Ics
Os tipos CD4042B contêm quatro circuitos de bloqueio, cada um estrobossado por um relógio comum.A impedância dos dispositivos de saída de canais n e p está equilibrada e todas as saídas são electricamente idênticas.
A informação presente na entrada de dados é transferida para as saídas Q e Q durante o nível CLOCK, que é programado pela entrada POLARITY.Para POLARIDADE = 0 a transferência ocorre durante o nível 0 RELOJO e para POLARIDADE = 1 a transferência ocorre durante o nível 1 RELOJOAs saídas seguem a entrada de dados, desde que os níveis CLOCK e POLARITY definidos acima estejam presentes. When a CLOCK transition occurs (positive for POLARITY = 0 and negative for POLARITY = 1) the information present at the input during the CLOCK transition is retained at the output until an opposite CLOCK transition occurs.
Os tipos de CD4042B são fornecidos em embalagens cerâmicas herméticas de dupla linha de 16 leads (subfixos F3A), embalagens de plástico de dupla linha de 16 leads (subfixo E), embalagens de contorno pequeno de 16 leads (D, DR, DT, DW, DWR,e sufixos NSR), e pacotes de contorno pequeno de encolhimento fino de 16 chumbo (sufixos PW e PWR).
Aplicações:
Armazenamento de buffer
Registo da exploração
Lógica digital geral
- Especificações:
| Categoria | Circuitos integrados |
| Calçados, fechaduras e registos | |
| Mfr | Instrumento do Texas |
| Série | CMOS Quad Clocked D Latch TI Ics |
| Pacote | Tray & Reel (TR) |
| Estatuto da parte | Atividade |
| PLL | - Sim, sim. |
| Propósito principal | Finalidade geral |
| Temperatura de funcionamento | -40°C ~ 85°C |
| Tipo de montagem | Montura de superfície/buraco de passagem |
| Embalagem / Caixa | SOIC/DIP |
| Número de base do produto | CD4042B CD4076B CD4508B CD54AC573 CD54ACT373 |
| Número de canais (#) | 4 |
| Família de Tecnologia | CD4000 |
| Voltagem de alimentação (min) (V) | 3 |
| Voltagem de alimentação (Max) (V) | 18 |
| Tipo de entrada | CMOS padrão |
| Tipo de saída | CMOS |
| Frequência de relógio (máximo) (MHz) | 8 |
| IOL (máximo) (mA) | 2.4 |
| IOH (máximo) (mA) | - Dois.4 |
| ICC (máximo) (uA) | 600 |
| Características | Velocidade padrão (tpd > 50 ns), Velocidade elevada (tpd 10-50 ns), Desligamento parcial (I-Off) |
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Classificações ambientais e de exportação:
| Atributo | Descrição |
|---|---|
| Estatuto da RoHS | Conformidade com a ROHS3 |
| Nível de sensibilidade à humidade (MSL) | 3 (168 horas) |
| Estatuto REACH | REACH Não afectado |
| Nomenclatura | EAR99 |
| HTSUS | 8542.39.0001 |
Envie o RFQ
Estoque:
In Stock
MOQ:
10pieces
