CD4042B CD4076B CD4508B CD54AC573 CD54ACT373 D Latch CMOS Cuadruple con Reloj TI Ic
Category:
Circuitos integrados
In-stock:
en stock
Price:
Negotiated
Payment Method:
T/T, Unión Occidental
Specifications
categoría:
Circuitos Componente-integrados electrónicos (IC)
Descripción:
Los tipos CD4042B contienen cuatro circuitos de enclavamiento, cada uno con luz estroboscópica media
Nombre de parte similar:
CD4042B CD4076B CD4508B CD54AC573 CD54ACT373
Serie:
Pestillos tipo D-COMS
Familia:
Flip-flops, pestillos y registros IC
Paquete:
Montaje en superficie/agujero pasante
Estado libre de plomo:
RoHS obediente, PB libre, sin plomo
Temperatura de funcionamiento:
-40 ° C ~ 85 ° C
Resaltar:
Circuitos Integrados CD4076B IC
,Circuitos Integrados CD4042B IC
,Circuitos Integrados CD4508B IC
Introducción
CD4042B CD4076B CD4508B CD54AC573 CD54ACT373 CMOS Quad Clocked D Latch TI Componentes Ic
Circuitos Integrados IC Texas Instruments(Componentes Electrónicos)
CD4042B CD4076B CD4508B CD54AC573 CD54ACT373 CMOS Quad Clocked D Latch TI Ics
Los tipos CD4042B contienen cuatro circuitos de latch, cada uno activado por un reloj común. Las salidas complementarias con búfer están disponibles desde cada circuito. La impedancia de los dispositivos de salida de canal n y p está equilibrada y todas las salidas son eléctricamente idénticas.
La información presente en la entrada de datos se transfiere a las salidas Q y Q durante el nivel de RELOJ que está programado por la entrada de POLARIDAD. Para POLARIDAD = 0, la transferencia ocurre durante el nivel de RELOJ 0 y para POLARIDAD = 1, la transferencia ocurre durante el nivel de RELOJ 1. Las salidas siguen la entrada de datos siempre que estén presentes los niveles de RELOJ y POLARIDAD definidos anteriormente. Cuando ocurre una transición de RELOJ (positiva para POLARIDAD = 0 y negativa para POLARIDAD = 1), la información presente en la entrada durante la transición de RELOJ se retiene en la salida hasta que ocurra una transición de RELOJ opuesta.
Los tipos CD4042B se suministran en paquetes cerámicos herméticos de doble línea en D (sufijos F3A), paquetes de plástico de doble línea en D (sufijo E), paquetes de contorno pequeño en D (sufijos D, DR, DT, DW, DWR y NSR) y paquetes de contorno pequeño delgado en D (sufijos PW y PWR).
Aplicaciones:
Almacenamiento de búfer
Registro de retención
Lógica digital general
- Especificaciones:
| Categoría | Circuitos Integrados (CI) |
| Flip-flops, latches y registros | |
| Fabricante | Texas Instrument |
| Serie | CMOS Quad Clocked D Latch TI Ics |
| Paquete | Bandeja y Carrete (TR) |
| Estado de la pieza | Activo |
| PLL | Sí |
| Propósito principal | Propósito general |
| Temperatura de funcionamiento | -40°C ~ 85°C |
| Tipo de montaje | Montaje en superficie/Agujero pasante |
| Paquete / Caja | SOIC/DIP |
| Número base del producto | CD4042B CD4076B CD4508B CD54AC573 CD54ACT373 |
| Número de canales (#) | 4 |
| Familia de tecnología | CD4000 |
| Voltaje de alimentación (Mín) (V) | 3 |
| Voltaje de alimentación (Máx) (V) | 18 |
| Tipo de entrada | CMOS estándar |
| Tipo de salida | CMOS |
| Frecuencia de reloj (Máx) (MHz) | 8 |
| IOL (Máx) (mA) | 2.4 |
| IOH (Máx) (mA) | -2.4 |
| ICC (Máx) (uA) | 600 |
| Características | Velocidad estándar (tpd > 50ns), Alta velocidad (tpd 10-50ns), Apagado parcial (Ioff) |
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Clasificaciones Ambientales y de Exportación:
| ATRIBUTO | DESCRIPCIÓN |
|---|---|
| Estado RoHS | Cumple con ROHS3 |
| Nivel de Sensibilidad a la Humedad (MSL) | 3 (168 Horas) |
| Estado REACH | REACH No Afectado |
| ECCN | EAR99 |
| HTSUS | 8542.39.0001 |
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Existencias:
In Stock
MOQ:
10pieces
